1. Field
The present teachings relate to reduction of distortion in electrical circuits. More particularly, the present teachings relate to a stacked linear power amplifier having capacitor feedback and resistor isolation.
2. Description of Related Art
Power amplifiers (PA) convert low-power signals into signals having a larger power. The prior art is replete with different PA designs and techniques for amplifying power. For example, J. Jeong, S. Pornpromlikit, P. M. Asbeck, D. Kelly, “A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs, IEEE Microwave and Wireless Components Letters, Vol. 16, No. 12, December 2006, discloses a serially-connected power amplifier (PA). See FIG. 1 of the present application, wherein a triple-stacked FET PA is shown. Jeong is concerned with obtaining large voltage swings at the gate of each FET and does so by providing the two top FETs with a capacitive voltage divider comprising the gate-to-source capacitance Cgs of each FET and an external gate capacitance C2, C3. C2 and C3 are determined so that each FET has the same drain-to-source (Vds), gate-to-source (Vgs), and drain-to-gate (Vdg) voltage swing. Jeong describes such arrangement to be essential, so that each FET delivers its maximum available power.
U.S. Pat. No. 6,137,367 to Ezzedine describes high power high impedance microwave devices for power applications. FIGS. 2 and 3 of Ezzedine show serially-connected PAs. In both embodiments, the Vds of each FET is the same.
U.S. Pat. No. 6,496,074 to Sowlati describes a cascode bootstrapped analog power amplifier circuit. FIG. 1 of Sowlati shows serially-connected FETs 10 and 12. Column 3, lines 60-65 of Sowlati states that use of the largest possible supply voltage is possible when Vds of 10 and 12 is the same.
U.S. Pat. No. 7,071,786 to Inoue describes a cascode circuit and an integrated circuit comprising such cascode circuit. As described at column 16 lines 60-65 of Inoue, the Vds of each FET should be the same.
However, in all of the above prior art examples of PA design, maximum available power appears to be the main concern. Non-linearity is therefore not addressed or improved, as non-linearity of serially connected transistors is usually amplified when the input signal experiences phase shifts as it passes from stage to stage. Therefore, while the above-described power amplifiers deliver the maximum available power, the linearity of the amplifiers is unfortunately unacceptable for many modern communication standards.
In particular, in accordance with modern communication standards, power spillover of PAs into adjacent allocated frequency channels should be taken into account. Non-linearity of the PA components is one of the main causes of power spillover, because it generates harmonics of the center frequency and produces intermodulation distortion (IMD). Therefore, there is a need to reduce non-linearity of the PA components as much as possible.